Multilayered box in fdsoi mosfets

ABSTRACT

A fully depleted MOSFET has a semiconductor-on-insulator substrate that includes a substrate material, a BOX positioned on the substrate material, and an active layer positioned on the BOX. The BOX includes a first layer of material with a first dielectric constant and a first thickness and a second layer of material having a second dielectric constant different than the first dielectric constant and a second thickness different than the first thickness. The first layer of material is positioned adjacent the substrate material and the second layer of material is positioned adjacent the active layer. Drain and source regions are formed in the active layer so as to be fully depleted. The drain and source regions are separated by a channel region in the active layer. A gate insulating layer overlies the channel region and a gate stack is positioned on the gate insulating region. It is anticipated that the structure is most useful for channel regions less than 90 nm long.

FIELD OF THE INVENTION

This invention relates in general to analog and digital devicesoperating at multi-gigahertz frequencies and/or nanometer length scaledimensions and to methods of fabrication.

The present disclosure relates to optimal design criteria and method offabrication of analog and digital devices based onsemiconductor-on-insulator (SOI) multilayered structures. In particular,electronic devices such as planar field-effect-transistors (FETs)utilizing fully-depleted semiconductor-on-insulator (FDSOI) substratesare specifically chosen as an example utility of the present structure.Direct application of the present structure is disclosed for planarsingle gate FDSOI FETs approaching the 45 nm technology node and below.

BACKGROUND OF THE INVENTION

Present silicon (Si) nanometer (nm) scale electronic devices areconstructed using planar FET topologies. The FET control gate iscomposed of a gate dielectric (usually an oxide and thus termed a‘gate-oxide’) and is typically composed of silicon dioxide (SiO₂) orsilicon oxy-nitride (SiO_(x)N_(y)) dielectric materials disposed upon asingle crystal silicon active layer and/or substrate. Modern logicdesign is based on complementary-metal-oxide-semiconductors (CMOS)employing charge carrier transport exhibiting both n-type and p-typeCMOSFETs and are characterized by transistor feature sizes in ranges of130 nm, 90 nm, 65 nm, 45 nm, 32 nm, and ultimately approaching 20 nm.Referring to FIG. 1, a graph is illustrated showing the actual andprojected CMOSFET length scale and gate length (Lg) required as afunction of technology generation (technology node) and year. As theplanar transistor geometry shrinks in accordance with new fabricationgenerations or technology nodes, all the CMOSFET dimensions must scale.For example, the gate oxide thickness and gate length must also bereduced (or scaled) in accordance with well known scaling rules. Theprimary advantage of CMOS logic gates is the logic elements (composed ofmany nMOS and pMOS transistors) only draw significant current betweenlogic state transitions, thereby allowing power consumption to begreatly minimized due to negligible dissipation in the off-state. Thisis clearly an advantage for high densities of logic elements inultra-large-scale integrated circuits (ULSICs), such as, microprocessorsand mobile and/or portable devices.

Projected performance gains of 30% per technology generation have beentargeted at increasing CMOSFET density and circuit function per unitarea. An added benefit of reduced feature scaling is that increasedMOSFET device and overall circuit speed occurs. Ideal device performancehas been relaxed due to deficiencies in materials and manufacturingmethods available, resulting in CMOSFET sub-threshold leakage currentincreasing continuously from several nanoamperes per micrometer (nA/μm)at the 130 nm technology node, to currently hundreds of nA/μm at the 65nm technology node. This leakage represents approximately two orders ofmagnitude increase in leakage power.

There are two types of leakage power in ULSICs: active leakage power andstandby leakage power. Active leakage power is defined as leakage powerconsumed by a nanoscale CMOS system while doing useful work and standbyleakage power is leakage power consumed when the system is idle.

The 90 nm technology node has seen leakage power increase to as much as40% of the total on-chip power consumed. The waste heat and/or powerdissipation situation degrades further with reduced CMOSFET lengthscaling to 65 nm and below. The leakage currents ultimately manifest asheat in ULSICs with large waste heat power densities and will soonexceed on-chip and off-chip conventional thermal management systems.Such large thermal loads result in reduced system reliability and placelimits on the battery lifetime of portable devices. Ultimately, thethermal problem due to leakage currents places hard thermodynamic limitson further CMOSFET feature size reduction, circuit density and increasedfrequency of operation.

The leakage currents in planar single gate CMOSFETs can be generallyclassed as leakage substantially through the control gate oxideinsulator and leakage between the channel layer and the substrate.

Sub-90 nm CMOSFET channel length scaling requires conventional gateoxide insulator thickness (L_(GOX)) to approach only a few atomiclayers. Such small physical thickness of L_(GOX) is causing a failing ofthe ideal insulator action of the gate oxide due to quantum mechanicaltunneling processes. This gate oxide tunneling current adversely affectsthe off-state and on-state leakage and the mobility of the fundamentalcarriers, electrons (nMOS) and holes (pMOS). Unfortunately, replacingthe gate oxide with an ideal higher dielectric constant (i.e., high-κ)material in order to satisfy the equivalent gate oxide thickness(EOT_(GOX)) required along with high reliability and fabricationcompatibility has not yet eventuated despite much effort and researchover the past decade.

Efforts to reduce channel to substrate leakage concentrated onimplementing partially depleted semiconductor-on-insulator (PDSOI)substrates. Historically, PDSOI is used as a solution to reduce deviceleakage currents and substrate capacitance. Unfortunately, the earlyadvantage of reduced capacitive coupling of the channel to the substrateusing PDSOI when incorporated in long gate length devices above the 90nm technology node has been superseded by more challenging factors forshort channel CMOSFET dimensions below the 65 nm technology node.

Scaling below the 65 nm technology node imposes many new constraints ondevice topology. In order to retain the fundamental electrostaticoperation of the CMOSFET devices below the 65 nm technology node, theuse of fully-depleted semiconductor-on-insulator (FDSOI) substrates arenecessary. Optimal FDSOI design relies on an understanding of the uniqueperformance advantages provided by both the ultrathin semiconductoractive layer (or body) and the buried insulator layer. Conventionalsemiconductor-on-insulator substrates use silicon-on-insulator (SOI)structure.

Classical bulk-Si and PDSOI CMOS scaling beyond a physical gate lengthof ˜50 nm will probably no longer be valid due to severe short channeleffects (SCEs) and unacceptably low ratios between on and off currents(I_(on)/I_(off)). This is the primary reason for introducing single gate(SG) FDSOI devices initially at 65 nm. Toward the 32 nm technology node,or approximately thereat, planar and/or vertical double gate (DG) FDSOIdevices are required to preserve FET electrical integrity. Key issueseffecting planar single gate FDSOI are the introduction of high-κ gateoxides, gate contacts (e.g., metal gates), FDSOI physical structure andmanufacturability, source and drain contact resistance, and channelmobility.

One advantage not commonly remarked upon is the fact that SG FDSOIpotentially simplifies the ULSIC front-end-of-line (FEOL) process andpotentially the cost of manufacture. That is, bulk-Si and PDSOI CMOStypically use twin-wells to define the body of either the pMOS (using ann-well) and nMOS (using a p-well) because the substrate has a fixedconductive type. The gate threshold voltage can be adjusted via an-doped (or p-doped) poly-Si gate contact stacked onto the gate oxidefor n-MOS (or pMOS). P-type (or n-type) source and drain implants areused to realize p-MOS (or n-MOS) devices. It is well known by artisansin the field, the following FEOL steps are essential to the formation ofthe dual well CMOSFET process. First, a deep doping peak is formed usingion implantation techniques, so as to aid in the: (i) suppression oftransistor latch-up; (ii) reduce charge pairs generated from radiationeffects; and (iii) provide part of the electrostatic dischargeprotection path. The next critical FEOL step forms a shallow doping peaklocated just below the bottom of the shallow trench isolation regionsseparating FET devices. This step suppresses lateral leakage betweenadjacent transistors within the wells (intra-well leakage) and betweenadjacent transistors at the well boundaries (inter-well leakage). Thenext critical step forms another very shallow doping peak at the siliconsurface and is used to set the threshold voltage V_(th) of thetransistors. These steps are common to both bulk and PDSOI CMOSFETs.

The opportunity for fabrication process simplification using FDSOImainly occurs in the three preceding steps outlined above. The use ofFDSOI wafers eliminates the need for the high-energy ion implantationprocess that forms the deep n-type and p-type twin wells and the fieldchannel stop isolation regions. This translates directly into fewerphotolithographic masks and ion implantation steps, made possible by theelimination of well and field isolation implants.

CMOS transistors designed for use with SOI wafers are classified bythickness (designated L_(Si)) of the device-quality single-crystalsilicon layer at the surface of and extending above the buried oxide(BOX) insulator layer. The BOX layer is disposed upon a substrate,typically also composed of single crystal silicon. An SOI CMOStransistor is classified as partially depleted (PD) if the siliconsurface layer is thicker than the depth of the depletion region(designated L_(Depl)) in the transistor channel, i.e., L_(Depl)<L_(Si).The SOI CMOS is classified as fully depleted (FD) if the silicon surfacelayer is equal to the depth of the depletion region in the transistorchannel, i.e., L_(Depl)=L_(Si). Examples of short channel and longchannel FDSOI CMOSFET are illustrated in FIGS. 2A and 2B, respectively.The transistor will be partially depleted or fully depleted depending onthe silicon layer thickness above the BOX and the doping concentrationin the channel, designated N_(ch).

To form a FDSOI transistor, N_(ch) must be low enough so that the gatedepletion region extends throughout the entire thickness of the siliconactive layer. When the silicon surface layer in the SOI CMOS is thickerthan about 50 nm (L_(Si)>50 nm), the transistor will typically bepartially depleted, unless N_(ch) is reduced to such low values thatV_(th) is too low for practical CMOS applications. If the silicon layerthickness is reduced to L_(Si)<50 nm, the transistor will be fullydepleted, even when N_(ch) is increased to produce V_(th) considerablyhigher than bulk and PDSOI devices. If the silicon layer thickness isreduced further toward and below L_(Si)≦20 nm, the transistor willremain fully depleted even if N_(ch) is increased considerably toproduce even higher threshold voltages (e.g., V_(th)˜700 mV).

Significant advantages exist for FDSOI transistors over PDSOItransistors, and the trend in SOI CMOS beyond 90 nm is toward the use ofFD devices. A fundamental advantage in FDSOI CMOSFETs, is the parameterknown as the subthreshold slope (SS), which can attain values that canbe very low compared with bulk Si and PDSOI CMOSFETs. Typically, inFDSOI, a relatively small gate voltage, on the order of −50 mV increase,will result in a large, tenfold increase, in the subthreshold draincurrent. This allows V_(th) of the FDSOI CMOS device to be very low andto result in acceptable subthreshold leakage or off-state current(I_(off)). The low I_(off) determines the off-state power dissipation.Lowering V_(th) allows the supply voltage (V_(S)) to also be reducedsignificantly without degrading CMOS IC speed performance. This is afundamental property of FET scaling. A general rule of thumb requiresV_(S) to be greater or equal to 5V_(th). Typically, for V_(s)<5V_(th)the speed performance of the circuit will degrade rapidly. The reductionof V_(S) produces a significant reduction in active power dissipation,without high performance degradation. Note, the active power dissipationis further reduced by reduction of parasitic capacitance in SOI CMOSrelative to bulk CMOS.

In general, PDSOI CMOSFETs suffer problematic floating body effects,which is less of a problem in FDSOI transistors. Consequently, it isexpected that FDSOI CMOS transistors will be generally adopted in thenear future. Converting an existing PDSOI CMOS device and circuit designinto FDSOI CMOS is expected to be straightforward, at least incomparison with the challenges in the conversion from bulk CMOS to SOICMOS.

Using FDSOI devices, the short-channel effect is primarily controlled bythe thickness of the silicon film (L_(Si)), generally, the thinner thefilm, the better the control. Less than 20 nm of silicon should be usedat the 90 nm technology node and less than 15 nm of silicon should beused at the 65 nm technology node for planar single-gate fully depletedtransistors. Toward the end of the technology roadmap represented by the20 nm technology node, only L_(Si) ˜5 nm is required. This representssignificant manufacturing hurdles using conventional separation byimplantation of oxygen (SIMOX) and wafer bonding techniques. Directepitaxial techniques may provide significant advantages to SOI structureflexibility, uniformity and cost.

The electrostatic integrity (EI) advantage of single gate planar FDSOIMOSFETs compared to bulk Si MOSFETs is well known. FIG. 3 shows how thedimensionless figure of merit EI of planar single gate bulk Si, planarsingle gate FDSOI and double gate FDSOI MOSFETs scale as a function ofthe technology node. The required L_(Si) for SG and DG FDSOI MOSFETs isalso shown on the left hand axis of FIG. 3 as a function of thetechnology node.

Clearly, with reference to EI performance, the advantage of the SG FDSOIdevice is that it has substantially lower value of EI compared tobulk-Si for all technology nodes. Bulk-Si exhibits an unacceptably highvalue of EI (EI˜0.14) approaching and beyond the 65 nm technology node.The EI of SG FDSOI at the 45 nm technology node becomes equivalent tobulk-Si at the 65 nm technology node. SG and DG FDSOI structures arerequired to have ultra-thin Si body layer thickness in the range of 4nm≦L_(Si) 25 nm, the mid to lower bound approaching the 20 nm technologynode exhibiting quantum confinement effects. In prior art, L_(Si) hastypically been treated with the design parameters of the buried oxide(BOX) insulating layer as semi-infinite in extent. That is, the BOXlayer has typically remained unchanged in the thick layer regime,L_(BOX)>50-100 nm. The BOX layer is typically thick (t_(BOX)≧50-100 nm)so that the channel to BOX capacitance (C_(BOX)) is kept small relativeto the gate oxide capacitance (C_(GOX)), such that C_(BOX)<<C_(GOX). Thetrade-off between the short-channel effect, drain-induced barrierlowering and C_(GOX) by varying the BOX layer thickness (t_(BOX)) anddielectric constant have not been investigated in depth.

Furthermore, for FDSOI substrates both the Si and BOX layers have aroadblock for manufacture using prior art techniques approaching 2011,with 15 nm≦L_(Si)≦28 nm and 26 nm≦Si and BOX layers is an importantparameter for guarantee of MOSFET performance across a wafer. Therefore,techniques that allow relaxation of design manufacture tolerances arenecessary to reduce cost and increase yield.

It would be highly advantageous, therefore, to remedy the foregoing andother deficiencies inherent in the prior art.

Accordingly, it is an object of the present invention to provide new andimproved methods and apparatus for controlling short channel effects,leakage, and threshold effects of FDSOI MOSFETs including variouscombinations and positions of multilayer thin BOX, low-κ designs, andhigh-K designs.

An aspect of the present invention is to disclose methodology forcontrolling short channel effects and/or leakage and/or thresholdeffects of FDSOI MOSFETs advantageously using multilayer thin BOX and/orlow-κ designs.

Another aspect of the present invention is to disclose methodology forcontrolling short channel effects and/or leakage and/or thresholdeffects of FDSOI MOSFETs advantageously using multilayer thin BOX and acombination of low-κ and high-κ designs.

A further aspect of the present invention is to disclose methodology forcontrolling short channel effects and/or leakage and/or thresholdeffects of FDSOI MOSFETs advantageously using multilayer thin BOX and/orlow-κ designs with a conducting layer or layers disposed between the BOXlayers and the substrate.

SUMMARY OF THE INVENTION

Briefly, to achieve the desired objects and aspects of the instantinvention in accordance with a preferred embodiment thereof, provided isan SOI structure including substrate material, a BOX positioned on thesubstrate material, and an active layer positioned on the BOX. The BOXincludes a first layer of material with a first dielectric constant anda first thickness and a second layer of material having a seconddielectric constant different than the first dielectric constant and asecond thickness different than the first thickness. The first layer ofmaterial is positioned adjacent the substrate material and the secondlayer of material is positioned adjacent the active layer. In thepreferred embodiment, the first layer of material has a dielectricconstant lower than the dielectric constant of SiO₂.

In another embodiment in accordance with the present invention an SOIstructure includes substrate material, a BOX positioned on the substratematerial, and an active layer positioned on the BOX. The BOX includes afirst layer of material with a first dielectric constant and a firstthickness, a second layer of material having a second dielectricconstant different than the first dielectric constant and a secondthickness different than the first thickness, and a third layer ofmaterial having a third dielectric constant different than the seconddielectric constant and a third thickness different than the secondthickness. The first layer of material is positioned adjacent the singlecrystal substrate material, the third layer of material is positionedadjacent the active layer, and the second layer of material issandwiched between the first layer of material and the second layer ofmaterial. In a preferred embodiment of this structure, the first layerof material has a dielectric constant lower than the dielectric constantof SiO₂ and the second layer of material has a dielectric constanthigher than the dielectric constant of SiO₂.

The desired objects and aspects of the instant invention are furtherrealized in accordance with a method of manufacturing a short channelfully depleted device on an SOI structure. The method increasesperformance of the manufactured devices and alleviate manufacturingtolerances to simplify manufacturing processes. Generally, the methodincludes the steps of providing a substrate, forming a BOX in thesubstrate with an active layer on the BOX, and adjusting the dielectricconstant of at least a portion of the BOX to be lower than thedielectric constant of SiO₂ so as to reduce the subthreshold slope andthe drain-induced-barrier-lowering effect associated with the BOX.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and further and more specific objects and advantages ofthe instant invention will become readily apparent to those skilled inthe art from the following detailed description of a preferredembodiment thereof taken in conjunction with the drawings, in which:

FIG. 1 is a graph illustrating actual and projected CMOSFET length scaleand gate length required as a function of technology generation and oryear;

FIG. 2A illustrates a planar single gate FDSOI MOSFET structure withshort gate length;

FIG. 2B illustrates a planar single gate FDSOI MOSFET structure withlong gate length;

FIG. 3 is a graph illustrating electrostatic integrity versus technologynodes for bulk-Si, single-gate FDSOI, and double-gate FDSOI MOSFETs;

FIG. 4A illustrates a short channel thin box FDSOI;

FIG. 4B illustrates a short channel thick box FDSOI;

FIG. 5A illustrates drain-induced-barrier-lowering (DIBL) effects in ashort channel FDSOI MOSFET;

FIG. 5B illustrates drain-induced-barrier-lowering (DIBL) effects in along channel FDSOI MOSFET;

FIG. 6A illustrates two-dimensional electric field fringing in a shortchannel FDSOI MOSFET with a thin BOX layer;

FIG. 6B illustrates two-dimensional electric field fringing in a shortchannel FDSOI MOSFET with a thick BOX layer;

FIG. 7 illustrates an equivalent capacitance circuit for a planar singlegate FDSOI MOSFET;

FIG. 8 is a graph showing a typical drain current versus gate voltagetransfer curve for a planar single gate FDSOI MOSFET;

FIG. 9 is a graph showing subthreshold slope (SS) versus BOX layerthickness for the case of long and short channel FDSOI MOSFETs;

FIG. 10 is a graph showing the subthreshold slope versus L_(BOX) withsuperimposed competing effect due to DIBL through the BOX layer;

FIG. 11 is a graph showing the combined effect of C_(BOX) and DIBL_(BOX)on the subthreshold slope versus L_(BOX) for short channel FDSOIMOSFETs;

FIG. 12A illustrates the DIBL_(BOX) in a thin BOX FDSOI device with noground plane;

FIG. 12B illustrates the reduction of DIBL_(BOX) in a thin BOX FDSOIdevice with ground plane;

FIG. 13 is a graph showing the subthreshold slope versus L_(BOX) for asingle gate short channel FDSOI device;

FIG. 14 is a graph showing the short channel FDSOI subthreshold slopeversus the equivalent oxide thickness (EOT) of the BOX due to CBOX andDIBL_(BOX) for various dielectric constant BOX compositions;

FIG. 15A illustrates electric field fringing for short channel FDSOIdevice using high-κ BOX layer;

FIG. 15B illustrates electric field fringing for short channel FDSOIdevice using low-κ BOX layer;

FIG. 16A illustrates the equivalent oxide thickness (EOT) of a capacitorstructure using low-κ dielectric material, referenced to SiO₂;

FIG. 16B illustrates the equivalent oxide thickness (EOT) of a capacitorstructure using a high-κ dielectric layer, referenced to SiO₂;

FIG. 17 illustrates the equivalent oxide thickness (EOT) of a capacitorstructure using a mulilayered BOX structure (stacked) including high-κand low-κ dielectric layers, referenced to SiO₂;

FIG. 18 illustrate the equivalent oxide thickness (EOT) of anotherembodiment of a capacitor structure using a mulilayered BOX structure(stacked) including high-κ and low-κ dielectric layers, referenced toSiO₂;

FIG. 19 illustrates an embodiment of a short channel FDSOI device usinga multilayered BOX including high-κ and low-κ dielectric layers inaccordance with the present invention;

FIG. 20 illustrates another embodiment of a short channel FDSOI deviceusing a multilayered BOX including high-κ and low-κ dielectric layers inaccordance with the present invention;

FIG. 21A illustrates another embodiment of a short channel FDSOI deviceusing a thin multilayered BOX including high-κ and low-κ dielectriclayers in accordance with the present invention;

FIG. 21B illustrates another embodiment of a short channel FDSOI deviceusing a thick multilayered BOX including high-κ and low-κ dielectriclayers in accordance with the present invention;

FIG. 22 is a table of known low dielectric materials relative to SiO₂;

FIG. 23 illustrates an epitaxial process for fabricating short channellow-κ BOX FDSOI CMOSFETs; and

FIG. 24 illustrates a process using wafer bonding for fabricating alow-κ BOX region suitable for use in FDSOI CMOSFETs.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention discloses methods and apparatus for performanceoptimization of short channel and/or short gate lengthmetal-oxide-semiconductor field effect transistors (MOSFETs) on fullydepleted semiconductor-on-insulator (FDSOI) substrates viasimultaneously optimizing the semiconductor active layer thickness(L_(Si)), the channel doping concentration (N_(CH)), the buried oxidethickness (L_(BOX)), and the BOX dielectric constant (κ_(BOX)).Throughout this disclosure the term “BOX” is used to indicate a buriedinsulating structure including one or more layers of material (notnecessarily including an oxide) that forms a part of asemiconductor-on-insulator substrate hereinafter designated SOI. Also,while the substrate is usually composed of single crystal material, suchas silicon, other materials may be used and, accordingly, the region onwhich the BOX is situated is referred to herein as “substrate material”and may include anything that operates as a support for the BOX. It willbe understood that channel layers described herein are formed of singlecrystal semiconductor material such as silicon, germanium or othersemiconductor materials.

Turning now to FIG. 4, two types of short channel (L_(g)≦90 nm) FDSOIFETs using thin (L_(BOX)≦50 nm) and thick (L_(BOX)≧50 nm) BOX layers areillustrated. The source/drain regions, gate oxide and gate stack areotherwise identical. Conventional SOI fabrication technologies, such asSIMOX and wafer bonding (See FIGS. 23 and 24), can be used to fabricateBOX layers beneath thin single crystal Si active layer using any ofSiO₂, SiO_(x)N_(y), Si₃N₄, or combinations thereof. It is well known,that SiO₂ can form very low interface trap density with Si and has alower dielectric constant (κ=3.9) than Si₃N₄ (κ=6.8-7.5), depending onstoichiometry.

The use of high-κ gate oxides in short channel devices imposes furtherdesign criteria on the choice of the dielectric constant of the BOX. Forultrathin FDSOI channel layers (L_(Si)) and short channels or gates(L_(g)), the electric field between the gate and BOX are coupled throughthe active layer. The ratio of the gate oxide capacitance (C_(GOX)) tothe BOX capacitance (C_(BOX)) provides a measure of the strength ofcontrol that the top gate has relative to the BOX acting as a back orlower gate. C_(GOX)/C_(BOX)=(ε_(GOX)L_(BOX))/(ε_(BOX)L_(GOX)). For asingle gate FDSOI FET, the body factor (BF) can be defined asBF=1+(C_(CH-BG)/C_(G-CH)) where C_(CH-BG) is the capacitance between thechannel and the back gate and/or the substrate and C_(G-CH) is thecapacitance between the top-gate and the channel. The body factor is ameasure of the coupling between the gate voltage and the channel.Depending on the device bias configuration, C_(G-CH) is the lumpedrepresentation of the gate-to-channel capacitance and/or the presence ofa surface inversion channel. Similarly, C_(G-CH) represents the lumpedcapacitance that prevents the potential in the channel from beingcontrolled by the upper gate voltage. In an inversion mode FDSOI device,the channel is at the top or bottom portion of the Si active layer. Inan accumulation mode device, the Si body current flows wholly within theSi active layer with depth distribution controlled by the back-gatevoltage.

Therefore, a single gate FDSOI device generally has four modes ofoperation:

C_(G-CH)=C_(GOX) and C _(CH-BG) =C _(SOI) C _(BOX)/(C _(SOI) +C _(BOX));  (i)

C_(G-CH)=C_(GOX) and C _(CH-BG) =C _(SOI)=ε_(SOI) /L _(Si);  (ii)

C _(G-CH) =C _(GOX) C _(SOI)/(C _(GOX) +C _(SOI)) and C_(CH-BG)=C_(BOX);and  (iii)

C _(G-CH) =C _(GOX) C _(SOI)/(C _(GOX) +C _(SOI)) and C _(CH-BG) =C_(SC2) C _(BOX)/(C _(SC2) +C _(BOX)),  (iv)

where _(C) _(SC2) is the interface surface charge.

Clearly, the single gate has the greatest coupling to the BOX for allBOX thicknesses considered. The calculation uses SiO₂ for the gate oxideand the BOX and a heavily doped Si substrate, and can be thought of as agrounded BOX. The significance of the body factor is used as a figure ofmerit to quantify how well the gate controls the channel relative to theBOX. For reference, typical PDSOI planar single gate devices exhibitbody factors in a range of approximately 1.3 to 1.5. For equivalent gatelengths, the single gate FDSOI body factor is considerably lower than asingle gate PDSOI, however, the merit of the double gate is evident, dueto a larger coupling between the gates and the channel.

Typically, the GOX and BOX material compositions have been fixed at SiO₂and/or Si_(x)N_(y). That is, the difference in dielectric constantbetween the GOX and the BOX has been the same if not zero. The presentdisclosure further considers vastly different dielectric constantmaterials in the GOX and the BOX layers. For example, the introductionof a high-κ (e.g., κ(HfO₂˜22) GOX layer coupled to a FDSOI will markedlyalter the body factor if κ(GOX)>κ(BOX). If however, a high-κ material isused in the BOX and in the GOX (i.e., κ(GOX)=κ(BOX)) the body factorwill be essentially the same as for the conventional case ofκ(GOX)=κ(BOX)=κ(SiO₂) .

As device gate lengths scale below L_(g)≦90 nm, various short channeleffects become an issue for CMOSFET performance. In particular, the wellknown drain-induced-barrier-lowering (DIBL), severely influences thedrain potential on the channel region and deleteriously impacts theoperation of short channel MOS transistors. The effect is similar to thewell known punch-through effect. In the weak inversion regime there is apotential barrier between the source and the channel regions. The heightof this barrier is a result of the balance between drift and diffusioncurrents between these two regions. If a high drain voltage is applied,the barrier height can decrease, leading to an increased drain current.

The effect of DIBL for short and long channel planar single gate FDSOTdevices is illustrated in FIGS. 5A and 5B, respectively. The effect ofDIBL is relatively more pronounced in short channel devices compared tolong channel devices. Quantifiable effects are discussed later in thisdisclosure. The underlying process responsible for DIBL is related tothe BOX electric field fringing effect, shown in FIG. 6. The electricfield lines shown in FIGS, 6A and 6B are for the case of short channelFDSOI devices using thin and thick BOXs, respectively. In these examplesthe GOX and channel or active layers are assumed to be SiO₂ and Si,respectively. The dielectric material is assumed to be the same for thinand thick BOXs. Note, the GOX layer thickness is substantially thinnerthan the BOX layer for the case of a single gate FDSOI MOSFET.

The electric field fringing in the BOX, as illustrated in FIGS. 6A and6B, clearly shows that the electric field fringing in the BOX is reducedusing a thin BOX and therefore exhibits a lower DIBL effect. Physically,because of the thick BOX in conventional SOIs (L_(BOX)˜100-400 nm), theelectric field that emanates from the source/drain (S/D) junctiondepletion charge tends to terminate in the SOI body/channel, thusaugmenting the normal short channel effects (SCEs) due to the 2-Deffects in the SOI body and increasing the subthreshold. Based on thisphysical insight, a direct way to suppress the field fringing is toscale, or thin the BOX. However, for nanoscale gate lengths substantialthinning of the BOX is required e.g., t_(BOX)<25 nm. Such aggressivescaling of the BOX to circumvent the SCEs, increases the channel to BOXcapacitance which directly impacts CMOSFET speed. The breakdown of thesimple L_(Si) scaling with L_(g) can however be recovered by scalingL_(BOX) from thick regimes of 100 nm to the thin regimes less than 10nm. The hole mobility is also known to degrade in FDSOI CMOSFETs (whereL_(Si)=3.7-50 nm) using a thick BOX (1350 Å). The hole degradation isbelieved to result from the surface roughness scatter and spatialconfinement in the channel. This negatively impacts pMOS devices andeffects circuit performance. A potential solution is to reduce thespatial confinement by reducing the dielectric constant of the BOX andthus reduce interface scatter at the channel-BOX interface.

Therefore, a thin BOX FDSOI is preferable for reducing SCEs, however,increased body effect (e.g., BOX capacitance) results. The increase inBOX capacitance can be effectively reduced by incorporating a lowerdielectric material in the BOX relative to the GOX. For example, if GOXmaterial is SiO₂ and/or SiO_(x)N_(y), then a BOX layer using fluorinatedSiO₂ (FSG) is preferred. This can be incorporated as part of the waferbonding procedure.

Referring to FIG. 7, the equivalent capacitance circuit for a FDSOIMOSFET is illustrated. In FIG. 7 and the following discussion,C_(GOX)=gate oxide capacitance, C_(SOI)=Si layer or active layercapacitance, and C_(BOX)=buried oxide/insulator (BOX) capacitance.

Referring additionally to FIG. 8, a typical drain current (I_(D)) versusgate voltage (V_(G)) transfer curve is illustrated for a planar singlegate FDSOI MOSFET. An important parameter characterizing FDSOI devicesis the subthreshold slope or swing (SS), calculated from the inverseslope of the subthreshold drain current (I_(D)) versus gate voltage(V_(G)), given by: SS=d[V_(G)]/d[log(I_(D))]. Referring to FIG. 8, thesubthreshold slope is defined as the slope of the curve below thethreshold voltage.

Typically, the threshold current of a CMOSFET is independent of drainvoltage and due primarily to a carrier diffusion process. FIG. 7 depictsschematically the equivalent circuit of a FDSOI structure, and can beapproximated in terms of gate capacitance C_(GOX), channel capacitanceC_(SOI), and BOX capacitance C_(BOX). The surface charges at the gateoxide and Si channel interface, and the surface charges at the Sichannel and the BOX interface are denoted as C_(SC1) and C_(SC2),respectively. It can be shown that the subthreshold slope is wellapproximated by the relation:

SS=k_(B)Tq⁻¹ln(10){α−Γ/β}: where α=1+(C_(SC1)+C_(SOI))/C_(GOX);β=1+(C_(SC2)+C_(SOI))/C_(BOX); and Γ=C_(SOI)(C_(GOX)C_(BOX))⁻¹.

In a planar single gate FDSOI MOSFET, the substrate or region beneaththe BOX may also be used to bias the BOX so as to form an electricalback-gate. The GOX is biased via the gate contact and referred to as thefront-gate. Using the back-gate, the FDSOI device can be operated in thesubthreshold regime in either an enhancement-mode n-channel device(electron carriers) and/or an accumulation-mode p-channel device (holecarriers0. In the subthreshold regime, the back-gate may be used tocontrol various spatial regions within the device, namely: (i) theGOX-SOI surface inversion channel; (ii) the SOI-BOX inversion channel;(iii) the SOI channel current primarily disposed in a plane spatiallycloser to the GOX; and (iv) SOI channel current primarily disposed in aplane spatially closer to the BOX.

The lower limit of SS will be given by: SS_(L)=k_(B)Tq⁻¹ln(10){1+λ}:where λ=(C_(SOI)C_(BOX)){C_(GOX)(C_(SOI)+C_(BOX))}⁻¹The upper limit ofSS will be given by large and negative and positive back-gate bias suchthat accumulation and inversion occur at the interface between thechannel and BOX and is approximately given by:SS_(H)=k_(B)Tq⁻¹ln(10){1+θ}: whereθ=C_(BOX)(C_(SOI)+C_(GOX)){C_(SOI)C_(BOX}) ⁻¹.

Turning to FIG. 9, the effect on SS by varying LBOX and, thus, C_(BOX)(since C_(BOX)=ε_(BOX)/L_(BOX)) for the case of a homogeneous dielectricconstant ε_(BOX) layer. Curves representing SS versus L_(BOX) forvarious gate length device regimes, namely long (L_(g)>90 nm) and short(L_(g)≦90 nm) are shown. The FDSOI Si channel layer thickness L_(Si) isfixed. The SS in short channel devices is larger than for the case oflong channel devices for all L_(BOX) values considered. This may be adisadvantage for short channel FDSOI devices, but another competingeffect which tends to reduce the SS in short channel devices must beconsidered. The DIBL associated with the BOX, described previously, viathe 2-D electric field fringing through the BOX into the channel can beadequately described by

DIBL_(BOX) =a{(ε _(SOI)/ε_(GOX))L _(i) ⁻²[1+(L _(SOI) /L _(i))² ]L_(GOX) {L _(SOI)+3L _(BOX)(L _(i) −L _(SOI))(L _(i) −L _(SOI)+3L_(BOX))⁻¹ V _(dd)}+γΔDIBL_(BOX)

Where the thick BOX correction factor is given by:ΔDIBL_(BOX)=V_(dd)L_(i) ⁻³[L_(GOX)L_(Si)(L_(Si)+3L_(BOX))2−L_(i)²)^(0.5) and DIBL_(BOX)→0 for a thin BOX. Li is the length of theelectric field line and is underestimated by assuming it is equal to thegate length L_(g).

Turning now to FIG. 10, a comparison is shown of trends in SS due to theC_(GOX) via L_(BOX), and the DIBL effect through the BOX layer as afunction of L_(BOX). Clearly, the influence of C_(GOX) and DIBL_(BOX)counteract each other in the thin BOX regime (i.e., L_(BOX)<500 Å). Themagnitude of DIBL_(BOX) is reduced dramatically for the thin BOX regime.The total SS versus L_(BOX) characteristic is the combination of effectsdue to C_(BOX) and DIBL_(BOX). Referring additionally to FIG. 11, thecombined effect on SS resulting in a local minimum SS for thin BOXregimes is shown. All CMOSFET parameters other than L_(BOX) areequivalent. For the case of the GOX dielectric constant material beingmade from 65 nm technology node SiO_(x)N_(y) and the BOX layer beingmade from lower dielectric constant material, such as fluorinatedsilicon dioxide (F:SiO₂), the SS is minimized by choice of optimalL_(BOX)˜200-250 Å.

Advantageous termination of the electric field lines (as shown in FIGS.6A and 6B) penetrating the BOX is possible by positioning a highlyconductive doped semiconductor layer and/or ground plane immediatelybeneath the BOX and between the BOX and the substrate, as shown in FIG.12B. The effect of the electric field terminating ground plane is tofurther advantageously reduce DIBL_(BOX) for an otherwise equivalentL_(BOX). The electric field effect for no ground plane and for a groundplane is illustrated in FIGS. 12A and 12B, respectively.

The effect of the active layer thickness in the thin BOX short channelFDSOI device is also an important parameter influencing the SS for agiven BOX configuration. Referring to FIG. 13, a graph shows thereduction in SS for a planar single gate short channel (L_(g)<90 nm)FDSOI device by reducing L_(Si) from 250 Å to 40 Å, while keeping allother parameters constant. The optimal L_(BOX) required for minimum SS,generally shifts to lower L_(BOX) values for thinner L_(Si). However,the slope of the SS versus L_(BOX) curve to the left hand side of theL_(BOX) minimum increases faster for smaller L_(Si). This results inincreased sensitivity to BOX thickness fluctuations ΔL_(BOX).Conventional manufacturing tolerances for ΔL_(Si) and ΔL_(BOX) thicknessfluctuations are of the order ±5 nm using layer transfer and or waferbonding techniques and chemical mechanical polishing (CMP). Furthermore,active layer atomic cleaving techniques using hydrogen implantationintroduces large residual H-atom density in the active layer. Thisresidual hydrogen concentration typically peaks at the active layer-BOXinterface resulting in deleterious electrically active defects,potentially affecting long term device reliability and increasingC_(SC2) beyond acceptable levels.

One solution offered by the present invention is to alleviate thesensitivity of ΔL_(BOX) on SS by increasing the physical BOX thicknessrequired but keeping the equivalent BOX thickness (EOT) necessary forminimizing SS. This can be achieved by introducing a lower dielectricconstant insulator material immediately beneath the active layer. Thethickness of the low-κ BOX layer is determined by the relation given inFIG. 16, which will be described in more detail presently.

Using stoichiometric SiO₂ as the reference dielectric and/or insulatormaterial, the behavior of the SS due to C_(BOX) and DIBL_(BOX) areplotted as a function of L_(BOX) in FIG. 14. The short channel (L_(g)=20nm) FDSOI device is configured with a conventional GOX layer of SiO₂ anda Si active layer (L_(Si)=100 Å). The effect of reducing and increasingthe dielectric constant of the BOX layer relative to SiO₂ is shown inthe curves of FIG. 14. Increasing κ(BOX)>κ(SiO₂) results in an increasein the SS and DIBL_(BOX) for all L_(BOX) studied, due to an effectivereduction in the equivalent oxide thickness of the BOX. Conversely,decreasing κ(BOX)<κ(SiO₂) results in an overall decrease in the SS andDIBL_(BOX) for all L_(BOX) studied, due to an effective increase in theequivalent oxide thickness of the BOX. The net benefit of lowest SS istherefore obtained using a Low-κ BOX material, so that the SS isminimized beyond values attained using SiO₂.

Referring additionally to FIG. 15, the effect of using a high-κ andlow-κ BOX in a short channel FDSOI device is illustrated. As can be seenin FIG. 15, the 2-D electric field fringing effect is enhanced in thehigh-κ BOX case compared to an otherwise identical device using a low-κBOX. Conversely, the 2-D electric field fringing effect is reduced inthe low-κ BOX case compared to an otherwise identical device using ahigh-κ BOX. The net effect of using a low-κ BOX is to further reduce theDIBL_(BOX) effect. Conversely, the net effect of using a high-κ BOX isto further increase the DIBL_(BOX) effect. Therefore, the presentinvention teaches that the use of a complete and/or partial low-κ BOXlayer is advantageous for increasing the short channel FDSOI performanceand alleviating manufacturing tolerances of the SOI substrate structure.

Referring now to FIG. 16, a relation is shown between the equivalentoxide thickness (EOT) and the physical oxide thickness (L_(BOX))compared to reference material SiO₂. Clearly, EOT is reduced usinghigh-κ insulator and/or dielectric material. Conversely, EOT isincreased using low-κ insulator and/or dielectric material. Theimplication being that if a high-κ BOX is used it must be constructedphysically thicker than an equivalent optimal L_(BOX) using SiO₂.

Referring additionally to FIGS. 17 and 18, two implementations orembodiments are shown of different multilayer BOX structures composed ofdifferent dielectric constant materials. From the preceding explanationit is taught that the low-κ BOX is advantageous for use beneath thechannel. This technique is further used in the following example whereina low-κ layer forms only a portion of the total multilayered BOX.Further, it is disclosed that the low-κ layer is preferably positionedimmediately beneath the active channel layer, thereby separating theactive channel from the remaining BOX layers.

More specifically, FIG. 17 shows an example of an implementation inaccordance with the present invention using a multilayered high-κ andlow-κ structure forming a general capacitive device for purposes ofexplanation. It will be understood that the multilayered BOX structuresof FIGS. 17 and 18 are designed and constructed for use in asemiconductor device, such as a short channel FDSOI MOSFET. If the low-κlayer is positioned immediately beneath or adjacent the channel layer,the EOT will be dominated by the low-κ portion of the BOX. The advantageof this technique is that a high-κ BOX layer can be used with arelatively thin low-κ layer. Furthermore, one or more low-κ layers, andhigh-κ layers if desired, can be disposed in the multilayer BOX. Forexample, FIG. 18 illustrates two low-κ layers, one disposed immediatelyadjacent the channel layer and a second one disposed immediatelyadjacent the substrate material, with a relatively higher dielectricregion sandwiched between the two low-κ layers. Here it should beunderstood that the thickness of the low-κ layers do not need to beequivalent.

One embodiment in accordance with the present invention, illustrated inFIG. 19, is implemented by way of example in a short channel FDSOIMOSFET. In this embodiment a BOX 30 is positioned between substratematerial 32 and an active layer 34. BOX 30 includes a single low-κ layer36, positioned immediately below or adjacent active layer 34, and alayer 38 of relatively higher dielectric constant material positioned onor adjacent substrate material 32. A source region 40 and a drain region42 are formed in spaced apart relationship in active layer 34 with thespacing therebetween defining a channel region 44. A gate insulator(generally a gate oxide, GOX) layer 46 is positioned above channelregion 44 and a gate stack 48 (including a metal gate contact) ispositioned on gate insulator layer 46 to form a planar FDSOI MOSFET.

Another embodiment in accordance with the present invention, illustratedin FIG. 20, is also implemented by way of example in a short channelFDSOI MOSFET. In this embodiment similar components are designated withsimilar numbers and have a prime (′) added to indicate the differentembodiment. The difference between the embodiment illustrated in FIG. 19and the embodiment illustrated in FIG. 20 is the construction of theBOX. BOX 30′ includes a low-κ layer 36′, positioned immediately below oradjacent active layer 34′, and a layer 38′ of relatively higherdielectric constant material positioned immediately beneath low-κ layer36′. In this embodiment, another low-κ layer 39′ is positioned betweenrelatively high-κ layer 38′ and substrate material 32′. It should beunderstood by those skilled in the art that additional layers ofmaterial with different dielectric constants could be included in BOX 30or 30′ to provide additional or different characteristics.

Turning to FIGS. 21A and 21B, two additional embodiments according tothe present invention are depicted in short channel FDSOI MOSFETs. Inthese embodiments the thickness of the high-κ layer is adjusted to alterthe EOT. The implication mentioned in conjunction with FIG. 16 above isincluded in these embodiments to demonstrate variations of layerthicknesses.

In the embodiment illustrated in FIG. 21A, a BOX 50 is positionedbetween substrate material 52 and an active layer 54. BOX 50 includes asingle low-κ layer 56, positioned immediately below or adjacent activelayer 54, and a layer 58 of relatively higher dielectric constantmaterial positioned on or adjacent substrate material 52. A sourceregion 60 and a drain region 62 are formed in spaced apart relationshipin active layer 54 with the spacing therebetween defining a channelregion 64. A gate insulator (generally a gate oxide, GOX) layer 66 ispositioned above channel region 64 and a gate stack 68 (including ametal gate contact) is positioned on gate insulator layer 66 to form aplanar FDSOI MOSFET. The equivalent oxide thickness (EOT) for the thinBOX 50 is shown by double headed arrow 70.

The other embodiment in accordance with the present invention,illustrated in FIG. 21B, is also implemented by way of example in ashort channel FDSOI MOSFET. In this embodiment similar components aredesignated with similar numbers and have a prime (′) added to indicatethe different embodiment. The difference between the embodimentillustrated in FIG. 21A and the embodiment illustrated in FIG. 21B isthe construction of the BOX. In FIG. 21B, layer 58′ of relatively higherdielectric constant material is much thicker than layer 58 of FIG. 21A.The equivalent oxide thickness (EOT) for the thick BOX 50′ is shown bydouble headed arrow 70′. Thus, the EOT can be varied by varying thethickness of one or more of the multilayers in the BOX with the resultsexplained above.

Some exemplary candidate materials that exhibit lower dielectricconstants than SiO₂ are tabulated in the chart of FIG. 22. As can beseen from the candidate materials, the dielectric constant can besignificantly reduced below that of SiO₂ (κ=3.9) down to potentially anair gap (κ=1).

Turning now to FIG. 23, an epitaxial growth method in accordance withthe present invention is illustrated for fabricating or manufacturingsome or all of the embodiments disclosed. This method uses singlecrystal rare-earth oxides, rare-earth oxynitrides, and/or rare earthoxyphosphides that are epitaxially deposited in single crystal andsingle phase structures on a substrate. The rare earth materials andmethods are explained in more detail in one or more of the followingcopending United States Patent Applications, United States PatentPublications, and U.S. Pat. Nos.: 09/924,392; 10/666,897; 10/746,957;10/825,912; 10/825,974; 11/025,363; 11/025,681; U. S. Pub. 2005/0166834;U. S. Pub. 2005/0161773; U. S. Pub. 2005/0163692; U.S. Pat. Nos.11/054,573; 11/054,627; 11/253,525; 11/254,031; U.S. Pat. No.7,018,484;and U.S. Pat. No. 7,037,806 pertinent portions of eachincluded herein by reference.

In this method, the rare-earth based layer constitutes an insulatorand/or dielectric function. A single crystal semiconductor is thendeposited upon the insulator and/or dielectric thereby forming anepitaxial SOI structure. As explained in one or more of the abovedescribed documents, the rare earth material is deposited on the singlecrystal substrate material in single crystal form so that the singlecrystal semiconductor can be epitaxially grown thereon. As shown in FIG.23, the rare earth oxide layer is preferably deposited with a spatiallydependent oxygen concentration as a function of the growth direction.The oxygen concentration can be varied to be in excess or deficient soas to produce a variable stoichiometry rare-earth oxide layer. In oneexample, the oxygen excess region is chosen to reside in a regionsubstantially disposed away from the substrate and channel layers. Thatis, the central region of the rare-earth oxide is oxygen rich withchemical formula REO_(1.5+y), 0<y<1, where RE=rare earth chosen from thelanthanide series and O=oxygen. The regions immediately beneath theactive semiconductor layer and optionally above the substrate are chosento exhibit oxygen deficient chemical formula REO_(1.5−y), 0<y<1. Theepitaxial structure, including semiconductor-on-insulator, deposited ona substrate can then be optionally annealed and/or implanted with oxygenspecies so as to affect the formation of a lower dielectric constantlayer or region immediately beneath the top-most semiconductor activelayer.

Conversely, the epitaxial structure can be realized with oxygen richregions substantially at the beginning and end of the rare-earth oxidelayer deposition with the interior portion of the RE oxide substantiallyoxygen deficient. The epitaxial structure consisting ofsemiconductor-on-insulator, deposited on a substrate can then beoptionally annealed and/or implanted with oxygen species so as to affectthe formation of a lower dielectric constant layer or region immediatelybeneath the top-most semiconductor active layer.

Turning to FIG. 24, a process is illustrated for the formation of alow-κ BOX using wafer bonding techniques. A preferred embodiment is theuse of two single crystal silicon substrates, designated 241 and 242. Alow-κ dielectric layer 243 is deposited on the surface of siliconsubstrate 241. Low-κ dielectric layer 243 can, for example, be formed byfirst forming/depositing high quality SiO₂ followed by a fluorine ionimplantation and/or fluorine chemistry plasma immersion techniques. TheSiO₂ layer 243 is transformed into a fluorinated SiO₂ (F:SiO₂)composition with lower dielectric constant than the initial SiO₂ layer.Second silicon substrate 242 is optionally protected by a conventionalSiO₂ layer. Next, second substrate 242 is implanted with hydrogen and/orhelium atoms, designated 244, to the required density and depth so as toenable a blistering process for mechanical separation of bulk siliconsubstrate from the required silicon film 245. Substrates 241 and 242 arethen bonded together, with the exposed surface of silicon film 245bonded to the exposed surface of fluorinated SiO₂ layer 243, so as toattain intimate mechanical contact free from contamination andparticulate matter at the junction or interface. The bonded structure isthen annealed so as to activate atomic bonding between substrates 241and 242. An optionally separate anneal may be performed to initiate theblistering of the implanted atoms (or it may be initiated during thefirst anneal), thereby providing the separation of thin film 245 fromthe remaining bulk silicon of substrate 242. The completed structure isthen polished using CMP or multiple silicon oxidation and etch steps toreduce and polish the ultrathin silicon active layer 245 to the requiredthickness (40 Å≦L_(Si)≦250 Å) suitable for formation of semiconductordevices, such as FDSOI MOSFET or CMOSFETs. The completed structure,designated 246, is thus a FDSOI multilayer structure including a low-κBOX, due to the F:SiO₂ region. The BOX may optionally be composed ofmultilayer dielectric regions as disclosed above.

Thus, a new and improved SOI substrate for fully depleted small channeldevices is disclosed along with methods of manufacture. The SOIsubstrate includes a multilayer BOX with different numbers of layers inwhich the dielectric constant and the thickness of the various layerscan be specifically designed to increase performance of the manufactureddevices and alleviate manufacturing tolerances.

Various changes and modifications to the embodiments herein chosen forpurposes of illustration will readily occur to those skilled in the art.To the extent that such modifications and variations do not depart fromthe spirit of the invention, they are intended to be included within thescope thereof which is assessed only by a fair interpretation of thefollowing claims.

Having fully described the invention in such clear and concise terms asto enable those skilled in the art to understand and practice the same,the invention claimed is:

1-21. (canceled)
 22. A method of manufacturing a short channel fullydepleted device on an SOI structure, the method increasing performanceand alleviating manufacturing tolerances and including the steps of:providing a substrate; forming a BOX in the substrate with an activelayer on the BOX, the device having a subthreshold slope and the BOXhaving an associated drain-induced-barrier-lowering effect; andadjusting the dielectric constant of at least a portion of the BOX to belower than the dielectric constant of SiO₂ so as to reduce thesubthreshold slope and the drain-induced-barrier-lowering effectassociated with the BOX.
 23. A method as claimed in claim 22 wherein thestep of forming the BOX in the substrate and the active layer includesepitaxially fabricating the device.
 24. A method as claimed in claim 22wherein the step of forming the BOX in the substrate and the activelayer includes a wafer bonding technique.
 25. A method as claimed inclaim in claim 22 further including a step of forming the BOX with morethan one layer and the step of adjusting the dielectric constantincludes adjusting the dielectric constant of one layer of the more thanone layers.
 26. A method as claimed in claim in claim 25 wherein the ofstep of forming the BOX with more than one layer and the step ofadjusting the dielectric constant includes adjusting the dielectricconstant of one layer of the more than one layers immediately adjacentthe active layer.
 27. An SOI structure comprising: asemiconductor-on-insulator substrate including substrate material, a BOXpositioned on the substrate material, and an active layer positioned onthe BOX; and the BOX including a first layer of material with a firstdielectric constant and a first thickness and a second layer of materialhaving a second dielectric constant different than the first dielectricconstant and a second thickness different than the first thickness, thefirst layer of material being positioned adjacent the substrate materialand the second layer of material being positioned adjacent the activelayer, the dielectric constant of at least a portion of the BOX beinglower than the dielectric constant of SiO₂ so as to reduce adrain-induced-barrier-lowering effect associated with the BOX.
 28. AnSOI structure as claimed in claim 27 wherein the first dielectricconstant is higher than the second dielectric constant.
 29. An SOIstructure as claimed in claim 28 wherein the first dielectric constantis higher than the dielectric constant of SiO₂ and the second dielectricconstant is lower than the dielectric constant of SiO₂.
 30. An SOIstructure as claimed in claim 28 wherein the thickness of the firstlayer of material is greater than the thickness of the second layer ofmaterial.
 31. An SOI structure as claimed in claim 27 wherein the BOXincludes a third layer of material.
 32. An SOI structure as claimed inclaim 27 wherein the substrate material includes single crystalmaterial.
 33. An SOI structure as claimed in claim 32 wherein the singlecrystal material includes silicon.
 34. An SOI structure as claimed inclaim 27 wherein the active layer includes single crystal material. 35.A short channel fully depleted device on an SOI structure comprising: asemiconductor-on-insulator substrate including substrate material; a BOXin the substrate with an active layer on the BOX, the device having asubthreshold slope; and the BOX including a first layer of material witha first dielectric constant and a first thickness and a second layer ofmaterial having a second dielectric constant different than the firstdielectric constant and a second thickness different than the firstthickness, the first layer of material being positioned adjacent thesubstrate material and the second layer of material being positionedadjacent the active layer, the dielectric constant of at least a portionof the BOX being lower than the dielectric constant of SiO₂ so as toreduce the subthreshold slope and a drain-induced-barrier-loweringeffect associated with the BOX.